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www.irf.com 1 hybrid - high reliability radiation hardened dc/dc converter art28xxt series description features art 28v input, triple output the art series of three output dc/dc converters are designed specifically for use in the hostile radiation environments characteristic of space and weapon systems. the extremely high level of radiation tolerance inherent in the art design is the culmination of extensive research, thorough analysis and testing and of careful component specification. many of the best circuit design features characterizing the international rectifier standard product line were adapted for incorporation into the art topology. capable of uniformly high performance over long term exposures in radiation intense environments, this series sets the standard for distributed power systems demanding high performance and reliability. the art converters are hermetically sealed in a rugged, low profile package utilizing copper core pins to minimize resistive dc losses. long-term hermeticity is assured through use of parallel seam welded lid attachment along with international rectifier?s rugged ceramic pin-to-package seal. axial orientation of the leads facilitates preferred bulkhead mounting to the principal heat-dissipating surface. total dose > 100 krad (si), 2:1margin no see to let > 83 mev . cm 2 /mg derated per mil-std-975 & mil-std-1547 output power range 3 to 30 watts 19 to 50 volt input range input undervoltage lockout high electrical efficiency > 83% full performance from -55c to +125c continuous short circuit and overload protection 12.8 w/in 3 output power density true hermetic package external inhibit port externally synchronizable fault tolerant design 5v, 12v or 15 v outputs available manufactured in a facility fully qualified to mil-prf- 38534, class k, these converters are fabricated utilizing dscc qualified processes and are fully compliant to class k. the complete suite of pi tests has been completed including group c life test. variations in electrical, mechanical and screening specifications can be accommodated. contact ir santa clara for special requirements. pd-94529b
2 www.irf.com art28xxt series for notes to specifications, refer to page 3 input voltage -0.5v to 80v input voltage range 19v to 60v minimum output current 5% maximum rated 19v to 50v for full derating current, any output to mil-std-975 soldering temperature 300c for 10 seconds output power range 3w to 30 w storage temperature -65c to +135c operating temperature -55c to +125c absolute maximum/minimum ratings note1 recommended operating conditions note 2 specifications electrical performance -55c < t case < +125c, v in =28v, c l =0 unless otherwise specified. -55c to +85c for full derating to mil-std-975 parameter symbol conditions min max units output voltage accuracy v out i out = 1.5adc, t c = +25 c (main) i out = 250madc, t c = +25 c art2812(dual) i out = 250madc, t c = +25 c art2815(dual) 4.95 11.50 14.50 5.05 12.50 15.15 vdc output power note 5 p out 19 vdc< v in < 50vdc 3.0 30 w output current note 5 i out (main) 19 vdc< v in < 50vdc (dual) 150 75 3000 750 madc line regulation note 3 vr line 150 madc < i out < 3000 madc (main) 19 vdc< v in < 50vdc 75 madc < i out < 750 madc (dual) -15 -60 +15 +60 mv load regulation note 4 vr load 150 madc < i out < 3000 madc (main) 19 vdc< v in < 50vdc 75 madc < i out < 750 madc (dual) -180 -300 +180 +300 mv cross regulation note 8 vr cross (main) 19 vdc< v in < 50vdc (dual) -10 -500 +10 +500 mv total regulation vr all conditions of line, load, (main) cross regulation, aging, temperature and radiation art2812(dual) art2815(dual) 4.8 11.1 13.9 5.2 12.9 16.0 v input current i in i out = minimum rated, pin 3 open pin 3 shorted to pin 2 (disabled) 250 8.0 ma output ripple voltage note 6 v rip 19 vdc< v in < 50vdc i out = 3000 madc (main), 500 madc (dual) 70 mv p.p input ripple current note 6 i rip 19 vdc< v in < 50vdc i out = 3000 madc (main), 500 madc (dual) 100 ma p.p switching frequency f s sychronization input open. (pin 6) 225 275 khz efficiency eff i out = 3000 madc (main), 500 madc (dual) 83 %
www.irf.com 3 art28xxt series electrical performance (continued) 1. operation outside absolute maximum/minimum limits may cause permanent damage to the device. extended operation at the limit s may permanently degrade performance and affect reliability. 2. device performance specified in electrical performance table is guaranteed when operated within recommended limits. operati on outside recommended limits is not specified. 3. parameter measured from 28v to 19 v or to 50v while loads remain fixed. 4. parameter measured from nominal to minimum or maximum load conditions while line remains fixed. 5. up to 750 ma is available from the dual outputs provided the total output power does not exceed 30w. 6. guaranteed for a bandwidth of dc to 20mhz. tested using a 20khz to 2mhz bandwidth. 7. load current is stepped for output under test while other outputs are fixed at half rated load. 8. load current is fixed for output under test while other output loads are varied for any combination of minimum to maximum. 9. a capacitive load of any value from 0 to the specified maximum is permitted without comprise to dc performance. a capacitiv e load in excess of the maximum limit may interfere with the proper operation of the converter?s short circuit protection, causing erratic behavior dur ing turn on. 10. parameter is tested as part of design characterization or after design or process changes. thereafter, parameters shall be guaranteed to the limits specified in the table. 11. load transient rate of change, di/dt 2 a/sec. 12. recovery time is measured from the initiation of the transient to where v out has returned to within 1% of its steady state value. 13. line transient rate of change, dv/dt 50 v/sec. 14. turn on delay time is for either a step application of input power or a logical low to high transition on the enable pin (p in 3) while power is present at the input. notes to specifications parameter symbol conditions min max units enable input open circuit voltage drive current (sink) voltage range 3.0 0.1 -0.5 5.0 50.0 v ma v synchronization input frequency range pulse high level pulse low level pulse rise time pulse duty cycle external clock signal on sync. input (pin 4) 225 4.5 -0.5 40 20 310 10.0 0.25 80 khz v v v/ s % synchronization output pulse high level pulse low level signal compatible with synchronization input 3.7 0.0 4.3 0.25 v power dissipation, load fault p d short circuit, any output 16 w output response to step load changes notes 7, 11 v tld 10% load to/from 50% load 50% load to/from 100% load -200 -200 200 200 mv pk recovery time from step load changes notes 11, 12 t tld 10% load to/from 50% load 50% load to/from 100% load 200 200 s output response to step line changes notes 10, 11 v tln i out = 3000 madc (main) v in = 19 v to/from 50 v i out = 500 madc (dual) -350 -1050 350 1050 mv pk recovery time from step line changes notes 10, 11,13 t tln i out = 3000 madc (main) v in = 19 v to/from 50 v i out = 500 madc (dual) 500 500 s turn on overshoot v os (main) i out = minimum and full rated (dual) 100 500 mv turn on delay note 14 t dly i out = minimum and full rated 5.0 20 ms capacitive load notes 9, 10 cl (main) no effect on dc performance (dual) 500 100 f isolation iso 500vdc input to output or any pin to case (except pin 12) 100 m ?
4 www.irf.com art28xxt series group a tests v in = 28volts, c l =0 unless otherwise specified. notes to group a test table 1. parameter verified during dynamic load regulation tests. 2. guaranteed for dc to 20 mhz bandwidth. test conducted using a 20khz to 2mhz bandwidth. 3. load current is stepped for output under test while other outputs are fixed at half rated load. 4. each output is measured for all combinations of line and load. only the minimum and maximum readings for each output are re corded. 5. load step transition time 10s. 6. recovery time is measured from the initiation of the transient to where v out has returned to within 1% of its steady state value. 7. turn on delay time is tested by application of a logical low to high transition on the enable pin (pin 3) with power present at the input. 8. subgroups 1 and 4 are performed at +25oc, subgroups 2 and 5 at -55oc and subgroups 3 and 6 at +125oc. test symbol conditions unless otherwise specified group a subgroups min max units output voltage accuracy v out i out = 1.5 adc (main) i out = 250madc art2812(dual) i out = 250madc art2815(dual) 1, 2, 3 1, 2, 3 1, 2, 3 4.95 11.70 14.50 5.05 12.30 15.15 v output power note 1 p out v in = 19 v, 28v, 50 v 1, 2, 3 3.0 30 w output current note 1 i out (main) v in 19 v, 28v, 50 v (dual) 1, 2, 3 1, 2, 3 150 75 3000 500 ma output regulation note 4 vr i out = 150, 1500, 3000madc (main) v in = 19 v, 28v, 50 v i out = 75, 310, 625madc 2812(dual) i out = 75, 250, 500madc 2815(dual) 1, 2, 3 1, 2, 3 1, 2, 3 4.8 11.1 14.0 5.2 12.9 15.8 v input current i in i out = minimum rated, pin 3 open pin 3 shorted to pin 2 (disabled) 1, 2, 3 1, 2, 3 250 8.0 ma output ripple note 2 v rip v in = 19 v, 28v, 50 v i out = 3000ma main, 500ma dual 1, 2, 3 70 mv p-p input ripple note 2 i rip v in = 19 v, 28v, 50 v i out = 3000ma main, 500ma dual 1, 2, 3 100 ma p-p switching frequency f s synchronization pin (pin 6) open 4, 5, 6 225 275 khz efficiency eff i out = 3000ma main, 500ma dual 1 2, 3 83 81 % power dissipation, load fault p d short circuit, any output 1, 2, 3 16 w output response to step load changes notes 3, 5 v tl 10% load to/from 50% load 50% load to/from 100% load 4, 5, 6 4, 5, 6 -200 -200 200 200 mv pk recovery time from step load changes notes 5, 6 t tl 10% load to/from 50% load 50% load to/from 100% load 4, 5, 6 4, 5, 6 200 200 s turn on overshoot v os (main) i out = minimum and full rated (dual) 4, 5, 6 4, 5, 6 100 500 mv turn on delay note 7 t dly i out = minimum and full rated 4, 5, 6 5.0 20 ms isolation iso 500vdc input to output or any pin to case (except pin 12) 1 100 m ?
www.irf.com 5 art28xxt series radiation performance the radiation tolerance characteristics inherent in the art28xxt converter are the direct result of a carefully planned ground-up design program with specific radiation design goals. after identification of the general circuit topology, a primary task of the design effort was selection of appropriate elements from the list of devices for which extensive radiation effects data was available. by imposing sufficiently large margins on those electrical parameters subject to the degrading effects of radiation, designers were able to select appropriate elements for incorporation into the circuit. known radiation data was utilized for input to pspice and radspice in the generation of circuit performance verification analyses. thus, electrical performance capability under all environmental conditions including radiation was well understood before first application of power to the inputs. a principal design goal was a converter topology that, because of large design margins, had radiation performance essentially independent of normal elemental lot radiation completion of first article fabrication, screening and standard environmental testing was followed by radiation testing to confirm design goals. all design goals were met handily and in most cases exceeded by large margin. these test samples were built with elements that, with the foregoing exceptions, were not screened for radiation characteristics. additional radiation tests on subsequent art28xxt manufacturing lots provide continued confirmation of the soundness of the design goals as well as justification for the element selection criteria. the following table specifies guaranteed minimum radiation exposure levels tolerated while maintaining specification limits. performance variations. in the few instances where such margins were not assured, element lots were selected from which die were fabricated (and characterized) as radiation hard devices so that realization of the design goals could be assured. radiation specification t case = 25c test conditions min unit total ionizing dose (2:1 margin) mil-std-883, method 1019.4 operating bias applied during exposure 200 krad (si) dose rate temporary saturation survival mil-std-883, method 1021 1e8 1e11 rads (si)/sec heavy ions (single event effects) bnl dual van de graf generator 83 mev? cm2/mg
6 www.irf.com art28xxt series art28xxt circuit description figure i. art block diagram circuit description and application information the art28xxt series of converters have been designed using a single ended forward switched mode converter topology. (refer to figure i.) single ended topologies enjoy some advantage in radiation hardened designs in that they eliminate the possibility of simultaneous turn on of both switching elements during a radiation induced upset; in addition, single ended topologies are not subject to transformer saturation problems often associated with double ended implementations. the design incorporates a two-stage lc input filter to attenuate input ripple current. a low overhead linear bias regulator is used to provide bias voltage for the converter primary control logic and a stable, well regulated reference for the error amplifier. output control is realized using a wide band discrete pulse width modulator control circuit incorporating a unique non-linear ramp generator circuit. this circuit helps stabilize loop gain over variations in line voltage for superior output transient response. nominal conversion frequency has been selected as 250 khz to maximize efficiency and minimize magnetic element size. output voltages are sensed using a coupled inductor and a patented magnetic feedback circuit. this circuit is relatively insensitive to variations in temperature, aging, radiation and manufacturing tolerances making it particularly well suited to radiation hardened designs. the control logic has been designed to use only radiation tolerant components, and all current paths are limited with series resistance to limit photo currents. other key circuit design features include short circuit protection, undervoltage lockout and an external synchronization port permitting operation at an externally set clock rate. operating guidelines thermal considerations the art series of converters is capable of providing relatively high output power from a package of modest volume. the power density exhibited by these devices is obtained by combining high circuit efficiency with effective methods of heat removal from the die junctions. good design practices have effectively addressed this requirement inside the device. however when operating at maximum loads, significant heat generated at the die junctions must be carried away by conduction from the base. to maintain case temperature at or below the specified maximum of 125c, this heat can be transferred by attachment to an appropriate heat dissipater held in intimate contact with the converter base-plate. sample hold +15 return -15 +5 return short circuit pulse width modulator primary bias & reference emi filter under-voltage detector +input enable sync in input return sync out the circuit topology used for regulating output voltages in the art28xxt series of converters was selected for a number of reasons. significant among these is the ability to simultaneously provide adequate regulation to three output voltages while maintaining modest circuit complexity. these attributes were fundamental in retaining the high reliability and insensitivity to radiation that characterizes device performance. use of this topology dictates maintaining the minimum load specified in the electrical tables on each output. operating the converter without a load on any output will result in peak charging to an output voltage well above the specified voltage regulation limits, potentially in excess of ratings, and should be avoided. output load currents less than specification minimums will result in regulation performance that exceeds the limits presented in the tables. in most practical applications, this lower bound on the load range does not present a serious constraint; however the user should be mindfull of device performance when operated outside specified limits.
www.irf.com 7 art28xxt series effectiveness of this heat transfer is dependent on the intimacy of the baseplate-heatsink interface. it is therefore suggested that a heat transferring medium possessing good thermal conductivity is inserted between the baseplate and heatsink. a material utilized at the factory during testing and burn-in processes is sold under the trade name of sil-pad ? 400 1 . this particular product is an insulator but electrically conductive versions are also available. use of these materials assures optimum surface contact with the heat dissipater by compensating for minor surface variations. while other available types of heat conducting materials and thermal compounds provide similar effectiveness, these alternatives are often less convenient and are frequently messy to use. a conservative aid to estimating the total heat sink surface area (a heat sink ) required to set the maximum case temperature rise ( ? t) above ambient temperature is given by the following expression: a heat sink ? ? ? ? ? ? ? ? ? t p 80 594 085 143 . . . ? t pp eff out = ==? ? ? ? ? ? ? case temperature rise above ambient device dissipation in watts 1 1 where as an example, assume that it is desired to maintain the case temperature of an art2815t at +65c or less while operating in an open area whose ambient temperature does not exceed +35c; then ? t = 65 - 35 = 35c from the specification table, the worst case full load efficiency for this device is 80%; therefore the maximum power dissipation at full load is given by () p =? ? ? ? ? ? ? ? =? = 30 1 80 13002575 . ..w and the required heat sink area is a = 35 80 7.5 in heat sink 0.85 ? ? ? ? ? ? ? ?= ? 143 2 594 318 . .. 1 sil-pad is a registered trade mark of bergquist, minneapolis, mn thus, a total heat sink surface area (including fins, if any) of approximately 32 in 2 in this example, would limit case rise to 35c above ambient. a flat aluminum plate, 0.25" thick and of approximate dimension 4" by 4" (16 in 2 per side) would suffice for this application in a still air environment. note that to meet the criteria, both sides of the plate require unrestricted exposure to the ambient air. inhibiting converter output as an alternative to application and removal of the dc voltage to the input, the user can control the converter output by providing an input referenced, ttl compatible, logic signal to the enable pin 3. this port is internally pulled ?high? so that when not used, an open connection on the pin permits normal converter operation. when inhibited outputs are desired, a logical ?low? on this port will shut the converter down. an open collector device capable of sinking at least 100 a connected to enable pin 3 will work well in this application. figure ii. enable input equivalent circuit a benefit of utilization of the enable input is that following initial charge of the input capacitor, subsequent turn-on commands will induce no uncontrolled current inrush. 118k 2n2907a 150k enable input input return 150k 2n2222a 2n2222a v in 64k 186k 150k 5.6 v converter inhibit is initiated when this transistor is turned off 65k cr2
8 www.irf.com art28xxt series figure iii. synchronization input equivalent circuit output load fault protection parallel operation although no special provision for forced current sharing has been incorporated in the art28xxt series, multiple units may be operated in parallel for increased output power applications. the 5.0 volt outputs will typically share to within approximately 10% of their full load capability and the dual (15 volt) outputs will typically share to within 50% of their full load. load sharing is a function of the individual impedance of each output and the converter with the highest nominal set voltage will furnish the predominant load current. a minimum voltage is required at the input of the converter to initiate operation. this voltage is set to a nominal value of 16.8 volts. to preclude the possibility of noise or other variations at the input falsely initiating and halting converter operation, a hysteresis of approximately 1.0 volts is incorporated in this circuit. the converter is guaranteed to operate at 19 volts input under all specified conditions. input undervoltage protection input filter to attenuate input ripple current, the art28xxt series converters incorporate a two-stage lc input filter. the elements of this filter comprise the dominant input load impedance characteristic, and therefore determine the nature of the current inrush at turn-on. the input filter circuit elements are as shown in figure v. figure v. input filter circuit synchronization an additional feature is a synchronization output (pin 5) permitting multiple art28xx converters in a system to be synchronized to one of the converters in the set. see figure iv. the sync input port permits synchronization of an art converter to any compatible external frequency source operating in the band of 225 to 310 khz. the synchronization input is edge triggered with synchronization initiated on the negative transition. this input signal should be a negative going pulse referenced to the input return and have a 20% to 80% duty cycle. compatibility requires the negative transition time to be less than 100 ns with minimum pulse amplitude of +4.25 volts referred to the input return. in the absence of an external source, the converter will revert to its own internally set frequency. if external synchronization is not desired, the sync in pin may be left open (unconnected) permitting the converter to operate at its? own internally set frequency. figure iv. synchronization output equivalent circuit 6k 2n2222 4k 10pf sync output input return +10v 5 2 10k to internal clock an additional feature is a synchronization output (pin 5) permitting multiple protection against overload or short circuit on any output is provided in the art28xxt converter series. this protection is implemented by sensing primary switching current and, when a load fault condition is detected, pulse width is limited by the protection circuitry. the converter is able to operate continuously with a load fault witout damage or exceeding derating limits. 5k 2n2907a 10k 47pf sync input input return +10v pin 1 pin 2 34 h 5.4 fd 1.35 ? 4.7 h systems using multiple convertors may dictate operating the group at a common switching frequency. to accomodate this requirement, the art28xxt converters include a synchronization input (pin 4). topology is illustrated in figure iii.
www.irf.com 9 art28xxt series additional filtering figure vi. external input emi filter while the internal input filter of figure v keeps input ripple current below 100 ma p-p , an external filter may be applied to further attenuate this ripple to a level below the ce03 limits imposed by mil-std-461b. figure vi is a general diagram of the international rectifier filter module designed to operate in conjunction with the art28xx series converters to provide that attenuation. this circuit as shown in figure vi is constructed using the same quality materials and processes as those employed in the art28xx series converters and is intended for use in the same environments. this filter is fabricated in a complementary package style whose output pin configuration allows pin to pin connection between the filter and the converter. more complete information on this filter can be obtained from the arf461 data sheet. an external filter may also be added to the output where circuit requirements dictate extremely low output ripple noise. the output filter described by figure vii has been characterized with the art2815t using the values shown in the associated material list. it is important to be aware that when filtering high frequency noise, parasitic circuit elements can easily dominate filter performance. therefore, it is incumbent on the designer to exercise care when preparing a circuit layout for such devices. wire runs and lengths should be minimized, high frequency loops should be avoided and careful attention paid to the construction details of magnetic circuit elements. tight magnetic coupling will improve overall magnetic performance and reduce stray magnetic fields. +5 v 5v return +15v 15v return -15v +5v out +5v return +15v out 15v return -15v out c1 c2 c3 c4 c5 c6 c7 c8 l1 l2 l4 l3
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!! &$% ##! '()'#*+,' #- .(/!01 -2 !", #/#& !.(/! 01 -2 !-&", figure vii. external output filter measurement techniques can impose a significant influ- ence on results. all noise measurements should be mea- sured with test leads as close to the device output pins as physically possible. probe ground leads should be kept to a minimum length. although internal filtering is provided at both the input and output terminals of the art28xx series, additional filtering may be desirable in some applications to accommodate more stringent system requirements.
10 www.irf.com art28xxt series performance characteristics (typical @ 25c) figure viii. efficiency vs output power for three line voltages. figure ix. 5.0 v output regulation limits 0.3 a load on 15 v outputs 4.80 4.90 5.00 5.10 5.20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 5v load current, amps vout
www.irf.com 11 art28xxt series art28xxt case outline 5 4 3 2 1 8 9 10 11 12 13 14 2.400 1.400 2.700 0.150 3.25 ref. max 6 x 0.200 = 1.200 1.675 2.200 0.300 0.263 ? 0.136 - 6 holes 0.375 1.950 0.138 0.500 max mounting plane 0.040 pin dia. 0.050 flange 0.275 0.240 note: 1. dimensions are in inches. 2. base plate mounting plane flatness 0.003 maximum. 3. unless otherwise specified, tolerances are = 2 .xx = .01 .xxx = .005 4. device weight - 120 grams maximum. pin designation part numbering art 28 15 t / em model input voltage 28 = 28v 100 = 100v outputs t = triple output voltages 15 = 5v, 15v 12 = 5v, 12v screening level no suffix = flight /em = engineering radiation performance not specified for /em screened device type. note: pin # designation 1 + v input 2 input return 3 enable 4 sync in 5 sync out 8 no connection 9 - 15 vdc output 10 15 vdc output return 11 + 15 vdc output 12 chassis 13 + 5 vdc output 14 5 vdc output return
12 www.irf.com art28xxt series standard process screening for art28xxt series standard periodic inspections on art28xxt series inspection application quantity group a part of screening on each unit 100% group b each inspection lot 5 units group c first inspection lot or following class 1 change 10 units group d in line (part of element evaluation) as prescribed by mil-prf-38534 for option 2 world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 252-7105 ir santa clara: 2270 martin av., santa clara, california 95050, tel: (408) 727-0500 visit us at www.irf.com for sales contact information . data and specifications subject to change without notice. 08/2004 requirement mil-std-883 method /em limits no suffix limits (class k) temperature range -55c to +125c -55c to +125c element evaluation n/a mil-prf-38534 non-destructive bond pull 2023 n/a 100% internal visual 2017 temperature cycle 1010 cond c constant acceleration 2001, 500 g cond a pind 2020 n/a cond a burn-in interim electrical @ 160 hrs 1015 160 hrs @ 125c 320 hrs @ 125c (2 160 hrs) final electrical (group a) read & record data mil-prf-38534 & specification -55, +25, +125c -55, +25, +125c pda (25c, interim to final) n/a 2% radiographic inspection 2012 n/a seal, fine & gross 1014 cond a, c external visual 2009

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